1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with paged erase architecture. More particularly, the present invention relates to an improved architecture for an array of flash EEPROM cells with paged erase which includes multiple independent array ground circuits so as to provide greater endurance as well as enhanced performance.
2. Description of the Prior Art
In U.S. Pat. No. 5,077,691 to Sameer S. Haddad et al. issued on Dec. 31, 1991, there is disclosed a flash EEPROM array which has a negative gate voltage erase operation. The '691 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference in its entirety. One of the advantages obtained by applying a negative erase voltage through the wordlines to the control gates rather than applying a positive erase voltage through the source common line to the source regions of all memory cells in the flash EEPROM simultaneously is that erasure can be made to occur selectively on a row-by-row basis rather than having to erase all the memory cells of a chip simultaneously. Preferably, groups of rows are formed such that each group defining a sector provides a page-selectable erase block. For example, the memory array consisting of a large number, N.times.M (i.e., 1,000 or more) of such memory cells are typically formed on a single integrated circuit chip in an N.times.M matrix form, where N equals the number of columns and M equals the number of rows. If the matrix is assumed to have 1 million cells (i.e., 1024.times.1024), then groups of 128 rows each could be formed together so as to divide the matrix into eight sectors. Further, each of the sectors may be divided into two segments (left sector and right sector). Thus, the memory array could be typically formed of 16 half-sectors. Hence, the memory array could be erased selectively half-sector by half-sector for any given number of half-sectors rather than all memory cells being erased simultaneously.
In U.S. Pat. No. 5,126,808 to Antonio J. Montalvo et al. issued on Jun. 30, 1992, there is disclosed a flash EEPROM array with paged erase architecture. This '808 patent is assigned to the same assignee as in the present invention and is also hereby incorporated by reference in its entirety. With this paged erase architecture, during an erasure of a page a relatively high negative potential of -12 volts was applied to all of the control gates of the transistor cells via the word lines of the selected page for several hundred milliseconds. Further, the source regions of the transistor cells in the selected page were raised to a positive voltage of approximately +5.0 volts, and the drain regions thereof were allowed to float. Alternatively, the negative voltage could be applied to only a single word line in the selected page so as to selectively erase a single row. For all of the non-selected pages, the wordlines have 0 volts applied thereto. The problem encountered by this prior art architecture is that the transistor cells in the non-selected pages are still disturbed during the erasure of the selected page. This is because of the fact that even though the wordlines in the non-selected pages are grounded, the +5.0 volts applied to the source regions of the selected page is done through a common source line which is tied to the source regions of all transistor cells in the flash EEPROM array. Accordingly, the erase disturb will be generated in the array.
Moreover, it has been suggested in the '808 patent that a VCC level of +5.0 volts could be applied to all of the wordlines in the non-selected pages in order to eliminate completely this erase disturb (disturbing the charge stored on the floating gate). However, this technique created in turn a drawback which arises from the fact that the power dissipation per cell is increased since the capacitance of the control gate and source region must be charged and discharged. As a result, the power requirement of a memory array having one million or more memory cells (a megabyte chip) would be increased substantially. A second drawback in this prior art technique is encountered due to the cycling of charge back and forth on the transistor memory cells in the unselected sectors which will reduce its wear characteristics and eventually leads to physical damage.
In co-pending and commonly assigned U.S. application Ser. No. 07/964,807, now U.S. Pat. No. 5,282,170, to M. A. Van Buskirk et al. entitled "Negative Power Supply" and filed on Oct. 22, 1992, there is disclosed a negative power supply for generating and supplying a regulated potential to control gates of selected memory cell transistors through the wordlines during the flash erase mode of operation. This application Ser. No. 07/964,807, now U.S. Pat. No. 5,282,170 is also hereby incorporated by reference in its entirety. In FIG. 1 of the '807 application, there is shown a block diagram of the negative power supply 10 which includes an array VSS circuit 22 which is used to supply a VCC level of +5.0 volts to the source regions of the selected memory cells during erasure. A schematic circuit diagram of the array VSS circuit 22 is illustrated in FIG. 9 of the '807 application. The array VSS circuit 22 is used once for the entire memory array and provides only one global ground line VSS for the array. Accordingly, the same drawbacks discussed heretofore with respect to the '808 patent are likewise encountered in the '807 application.
The present invention represents a significant improvement over the prior art techniques of utilizing a single global ground line VSS for the memory array shown in the respective '808 patent and '807 application discussed above. The present invention includes a plurality of ground line circuits each generating a half-sector ground line signal. The source regions of all the memory cell transistors in each half-sector are connected to a separate independent ground line. Each of the separate independent ground lines is connected to one of the corresponding ground line circuits for receiving the associated half-sector ground line signal which is at a predetermined positive potential during flash erasure.